Differential amplifiers according to the prior art have a peaking frequency response which is dependent on a capacitor. For the amplifier to have a good common mode rejection ratio (CMRR), the impedances of the emitter current sources should remain high for all frequencies of operation for the amplifier. While it is generally not a problem to achieve this with modern high-speed bipolar processes, the presence of the capacitor does pose some difficulties with respect to the physical implementation of the circuit in a monolithic integrated circuit form.
The difficulty arises from the inherent inability to fabricate a true floating capacitor structure using a standard bipolar integrated circuit fabrication process. All known practical implementations result in some additional and unwanted parasitic capacitance between the capacitor structure and the external nodes, e.g. usually the substrate node of the integrated circuit. This unwanted parasitic capacitance appears as a shunt with the emitter current sources thereby causing a reduction in impedance, and a consequent reduction in the common mode rejection ratio of the amplifier when operating at high frequencies.
While small signal analysis of the amplifier may suggest that a high common mode rejection ratio can be maintained provided there is symmetry in the capacitor structure (i.e. leading to a cancellation of the unwanted common mode terms in the differential output), the non-linearities in the large-signal transfer function of the amplifier stage lead to an undesirable mixing of the common-mode and differential-mode signals. Under these conditions, the effective common mode rejection ratio can drop to an unacceptably low figure. Therefore, the physical implementation of a differential gain stage in a monolithic integrated circuit remains a problem.